In computing environments that utilize peripheral component interconnect express (PCIe) and other packet-based environments, latency may become an issue that hinders processing speeds of requests and data to and from an input/output (I/O) device. More specifically, in at least one nonlimiting example, latency can occur due to processing large and small read requests in a single pipeline. Similarly, in returning data for a request, latency can occur due to conversion of the requested data from a memory controller to the I/O device.